LXSPI¶
Register Listing for LXSPI¶
Register |
Address |
---|---|
LXSPI_BITBANG¶
Address: 0xe0007800 + 0x0 = 0xe0007800
Bitbang controls for SPI output. Only standard 1x SPI is supported, meaning the IO2 and IO3 lines will be hardwired to 1 during bitbang mode.
Field |
Name |
Description |
||||||
---|---|---|---|---|---|---|---|---|
[0] |
MOSI |
MOSI output pin, valid whenever dir is 0. |
||||||
[1] |
CLK |
Output value for SPI CLK line. |
||||||
[2] |
CS_N |
Output value of SPI CSn line. |
||||||
[3] |
DIR |
Dual/Quad SPI reuses pins SPI pin direction.
|
LXSPI_BITBANG_EN¶
Address: 0xe0007800 + 0x8 = 0xe0007808
Write a 1 here to disable memory-mapped mode and enable bitbang mode.