LXSPI
=====

Register Listing for LXSPI
--------------------------

+--------------------------------------------+--------------------------------------+
| Register                                   | Address                              |
+============================================+======================================+
| :ref:`LXSPI_BITBANG <LXSPI_BITBANG>`       | :ref:`0xe0007800 <LXSPI_BITBANG>`    |
+--------------------------------------------+--------------------------------------+
| :ref:`LXSPI_MISO <LXSPI_MISO>`             | :ref:`0xe0007804 <LXSPI_MISO>`       |
+--------------------------------------------+--------------------------------------+
| :ref:`LXSPI_BITBANG_EN <LXSPI_BITBANG_EN>` | :ref:`0xe0007808 <LXSPI_BITBANG_EN>` |
+--------------------------------------------+--------------------------------------+

LXSPI_BITBANG
^^^^^^^^^^^^^

`Address: 0xe0007800 + 0x0 = 0xe0007800`

    Bitbang controls for SPI output.  Only standard 1x SPI is supported,
    meaning the IO2 and IO3 lines will be hardwired to `1` during bitbang mode.

    .. wavedrom::
        :caption: LXSPI_BITBANG

        {
            "reg": [
                {"name": "mosi",  "bits": 1},
                {"name": "clk",  "bits": 1},
                {"name": "cs_n",  "bits": 1},
                {"name": "dir",  "bits": 1},
                {"bits": 4}
            ], "config": {"hspace": 400, "bits": 8, "lanes": 1 }, "options": {"hspace": 400, "bits": 8, "lanes": 1}
        }


+-------+------+-----------------------------------------------+
| Field | Name | Description                                   |
+=======+======+===============================================+
| [0]   | MOSI | MOSI output pin, valid whenever `dir` is `0`. |
+-------+------+-----------------------------------------------+
| [1]   | CLK  | Output value for SPI CLK line.                |
+-------+------+-----------------------------------------------+
| [2]   | CS_N | Output value of SPI CSn line.                 |
+-------+------+-----------------------------------------------+
| [3]   | DIR  | Dual/Quad SPI reuses pins SPI pin direction.  |
|       |      |                                               |
|       |      | +-------+-------------------------+           |
|       |      | | Value | Description             |           |
|       |      | +=======+=========================+           |
|       |      | | 0     | SPI pins are all output |           |
|       |      | +-------+-------------------------+           |
|       |      | | 1     | SPI pins are all input  |           |
|       |      | +-------+-------------------------+           |
+-------+------+-----------------------------------------------+

LXSPI_MISO
^^^^^^^^^^

`Address: 0xe0007800 + 0x4 = 0xe0007804`

    Incoming value of MISO signal.

    .. wavedrom::
        :caption: LXSPI_MISO

        {
            "reg": [
                {"name": "miso", "bits": 1},
                {"bits": 7},
            ], "config": {"hspace": 400, "bits": 8, "lanes": 1 }, "options": {"hspace": 400, "bits": 8, "lanes": 1}
        }


LXSPI_BITBANG_EN
^^^^^^^^^^^^^^^^

`Address: 0xe0007800 + 0x8 = 0xe0007808`

    Write a `1` here to disable memory-mapped mode and enable bitbang mode.

    .. wavedrom::
        :caption: LXSPI_BITBANG_EN

        {
            "reg": [
                {"name": "bitbang_en", "bits": 1},
                {"bits": 7},
            ], "config": {"hspace": 400, "bits": 8, "lanes": 1 }, "options": {"hspace": 400, "bits": 8, "lanes": 1}
        }